This invention pertains to a computer with a instruction set capable of handling unaligned references, and more particularly, the reading and writing of data having fractional word length, as well as a method for handling the same.
A new development in computer architecture has been the introduction of so called RISC (Reduced Instruction Set Computer) devices, in which each instruction is ideally performed in a single operational cycle. Such devices are advantageous over computers having standard architecture and instruction sets in that they are capable of much higher data processing speeds due to their ability to perform frequent operations in shorter periods of times. Frequently, computers and similar data processors must be able to handle data having fractional word length. For example, although many computers are designed to handle words two or four bytes in length (i.e., words of 16 or 32 bits each), certain peripheral devices and applications generate or accept data of only one or two bytes. This is often the case with data processing programs and products. One result of this type of data is that it produces an unaligned reference. Namely, for a machine capable of handling four-byte words (32 bit devices), if incoming data is located sequentially as two bytes of data followed by four bytes of data, the four bytes of data cannot be retrieved or stored in a single cycle because it would overlap a word boundary within the memory. This effect is even more problematical if a word overlaps a page boundary within the memory because, if a virtual memory system is used, only a portion of the word may actually reside in addressable memory. Therefore, prior art RISC devices either do not accept data in this form, in which case special procedures must be followed to ensure that all data is aligned in word boundaries, or very involved programming is required which uses up at least two consecutive instruction cycles. One way to ensure for example that all data is aligned in word boundaries would be to add extra bits to data of shorter length, usually known as bit stuffing. Whether bit stuffing is used or the programming is altered, it is obvious that unaligned references seriously degrade the performance of prior art RISC devices.
Also, it should be noted that data is organized in modern computers in either of two formats or in some combination of those formats. The formats are known as "big endian," in which the high order bit, byte, or other unit of information is located in the lower numbered unit address, and "little endian," in which the high order unit of information is located in the higher numbered unit address. Thus, in a true big endian computer architecture, bits of data are thought of as being lined up from left to right, the lowest numbered and most significant bit being on the left. When this string of bits is divided into, for example, 8-bit bytes, 16-bit halfwords, and/or 32-bit words, the lowest numbered and most significant byte, halfword, or word continues to be located on the left. In a true little endian architecture, the scheme is exactly the opposite. Bits, bytes, halfwords, and words are numbered right to left, the least significant bit, byte, halfword, or word being located on the right.